Thin film resistance testing is a crucial step in material characterization and semiconductor process control, and its accuracy directly affects the evaluation of material electrical properties. The test results are influenced by multiple factors and need to be systematically analyzed from the aspects of sample characteristics, testing conditions, instrument parameters, operating standards, and environmental factors.

1、 The influence of intrinsic characteristics of samples

1. Film uniformity

-Thickness fluctuation: Local thickness differences can lead to uneven spatial distribution of resistance values (such as thickness gradients at the edges of sputtered thin films).

-Composition gradient: Differences in target sputtering yield or changes in deposition rate may cause component concentration gradients (such as the radial distribution of In/Sn ratio in ITO thin films).

-Grain size: The grain boundary scattering effect of polycrystalline thin films significantly affects carrier mobility (such as a 30% increase in resistivity when the grain size of AZO thin films is>50nm).

2. Surface state and interface characteristics

-Oxide layer: Metal thin films exposed to air may form insulating oxide layers (such as Al ₂ O3 on the surface of Al thin films, which increases the square resistance by 5-10 times).

-Roughness: For every 1nm increase in Ra value, the contact resistance of the probe may increase by 10-15% (AFM detection shows a loss rate of 12% in the contact area of rough surfaces).

-Adsorption effect: Organic pollution layers (such as fingerprint grease) can reduce surface resistance by two orders of magnitude.

3. Stress state

-Tensile stress leads to lattice distortion and enhanced carrier scattering (such as an 8% increase in resistivity when Si thin film stress>1GPa).

-Stress induced cracks can form leakage channels (such as a 3-fold increase in leakage current under compressive stress in TaN thin films).

2、 The impact of testing conditions

1. Temperature effect

-Temperature Coefficient of Resistance (TCR): The TCR of metal thin films is about+0.3%/K, while that of semiconductor thin films can reach -2%/K.

-Joule heating: Under a test current of 10mA, the temperature rise of a 100 Ω film can reach 5K/min, resulting in dynamic resistance drift.

-Phase transition risk: Some oxide thin films (such as VO ₂) undergo a metal insulator transition near the Curie temperature.

2. Humidity and Atmosphere

-Moisture absorbing films (such as NaCl doped polymers) experience a 40% decrease in resistance when RH>60%.

-The reducing atmosphere (H ₂/Ar) can alter the surface state of noble metal thin films (such as Au).

-Corrosive environments (such as Cl ₂) cause a 15% increase in silver film resistance per hour.

3. Mechanical loading

-Probe pressure: Under the Young's modulus of silicon wafer, a pressure change of 0.1N causes a fluctuation of ± 3% in contact resistance.

-Scratch damage: Plastic deformation may occur when the probe moves laterally at a speed greater than 1 μ m/s.

-Clamping stress: When the clamping force of PC film is greater than 0.5MPa, a piezoresistive effect occurs (Δ R/R reaches 1.2%).

3、 The influence of instrument parameters

1. Electrical incentives

-Current mode: Constant current source is superior to constant voltage source, and the nonlinear error within the range of 10nA-10mA is less than 0.5%.

-Frequency response: During AC testing, capacitive impedance will be introduced in the frequency band above 1kHz (such as Si ∝ N ₄ thin film dielectric constant influence>10%).

-Polarization effect: When the DC bias is greater than 1V, ferroelectric thin films (such as PZT) will undergo directional polarization.

2. Geometric configuration

-Four probe method: The probe spacing error of ± 1 μ m leads to a block resistance error of ± 0.5% (based on the van der Waals correction formula).

-Linear contact: The curvature radius of the probe needs to be<10 μ m to ensure ohmic contact (the proportion of contact resistance in graphene testing should be<10%).

-Edge effect: When the sample size is less than 5 times the probe spacing, a circular electrode correction (error compensation rate>92%) is required.

3. Data collection

-Sampling rate: Transient measurements require>1MS/s to capture switch characteristics (such as MoS ₂ transistor turn-on process).

-Noise level: 1 μ V level noise can mask high impedance thin film (ρ>10 ⁶Ω· cm) signals.

-Integral time: The lock-in amplification technology can increase the signal-to-noise ratio by 3 orders of magnitude.

4、 The shadow of operational standards

1. Sample preparation

-Cleaning process: RCA cleans residual organic matter to increase contact resistance by 15-20 Ω.

-Annealing treatment: Rapid annealing (RTA) causes a fluctuation of defect concentration by ± 8% (XRD half width change of 0.1 °).

-Photolithography alignment: When the mask deviation is greater than 2 μ m, the geometric correction factor error of the Hall stripe sample reaches 5%.

2. Testing process

-Pre pressure stage: 50gf pre pressure can eliminate the surface oxide layer (AES detection shows a 40% decrease in oxygen content).

-Scanning path: The in-plane anisotropic thin film needs to undergo vector testing along the crystal direction/growth direction.

-Multiple measurements: The dispersion of repeated tests at the same location should be<3 σ (typical requirement is CV value<2%).

5、 Environmental interference factors

1. Electromagnetic interference

-50Hz power frequency interference: When unshielded, the amplitude of low-frequency noise can reach 10 μ V.

-Electrostatic discharge: When the human body's static electricity exceeds 3kV, it may penetrate thin gate dielectrics (such as the gate oxide layer of GaN HEMT devices).

-Ground loop current: Poor grounding of multiple devices can generate microampere level interference current.

2. Mechanical vibration

-0.1g vibration acceleration causes probe displacement noise>10nm (detected by laser interferometer).

-Acoustic interference: An environment with noise levels greater than 80dB can cause a sub micron level positioning deviation of ± 50nm.

6、 Data correction and processing

1. Geometric correction

-Non circular samples require an ellipse correction factor (error compensation range of 0.1-1.5%).

-The step structure test needs to deduct the substrate contribution (such as SiO ₂/poly Si stacked structure).

2. Contact resistance correction

-In TLM testing, the slope error of linear fitting should be less than 0.5% (R ²>0.999).

-The four probe method requires verification of the I-V linear region (data invalid when nonlinearity>5%).

3. Temperature drift compensation

-Platinum resistance thermometer (Pt100) needs to achieve a resolution of 0.01K.

-Real time Kelvin connection can eliminate lead resistance (typical value of 2 Ω reduced to 0.1 Ω).