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Kerui Equipment Co., Ltd
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Kerui Equipment Co., Ltd

  • E-mail

    1617579497@qq.com

  • Phone

    13916855175

  • Address

    Room 902, No. 3 Baiyulan Environmental Protection Plaza, Lane 251, Songhuajiang Road, Yangpu District, Shanghai

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Calibration wafer standard wafer

NegotiableUpdate on 12/22
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Overview
Calibration wafer standards, used for calibration wafer standards and absolute calibration standards of Tencror Sufscan, Hitach, KLA Tencor and other equipment.
Product Details

Calibration wafer standard waferIt is a PSL wafer standard wafer that complies with NIST (National Institute of Standards and Technology) standards and contains a size certificate. The surface of the calibration wafer standard sheet is deposited with monodisperse polystyrene latex beads, and narrow peaks with a width of 50nm to 10 microns are formed to calibrate the equipment, completing the particle size response curve calibration of Tencor Surfscan 6220 and 6440, KLA Tencor Surfscan SP1, SP2, and SP3 wafer detection systems and other equipment. The calibration wafer standard wafer department deposits wafers in a full wafer deposition manner, where there is only a single particle size on the entire wafer. Alternatively, the calibration wafer standard can be deposited using multi-point deposition to form single or multiple size standard peaks, and accurately distributed within the calibration wafer standard.

Our company provides calibration wafer standard plates using standard particles. This can help customers complete the calibration of the dimensional accuracy of the equipment, including KLA-Tencor Surfscan SP1、KLA-Tencor Surfscan SP2、KLA-Tencor Surfscan SP3、KLA-Tencor Surfscan SP5、KLA-Tencor Surscan SP5xp、Surfscan 6420、Surfscan 6220、Surfscan 6220、ADE、Hitachi Tools such as Topcon SSIS and wafer inspection systems. Our 2300 XP1 particle deposition system can use PSL latex balls (polystyrene latex standard particles) and silica standard particles to deposit on 100mm, 125mm, 150mm, 200mm, and 300mm silicon wafers.

The semiconductor metrology equipment administrator at the factory uses these PSL calibration wafer standards to calibrate the size response curves of scanning surface inspection systems (SSIs) from KLA Tencor, Topcon, ADE, and Hitachi. PSL wafer standards are also used to evaluate the uniformity of Tencor Surfscan scanning of silicon wafers or films.

The calibration wafer standard is used to verify and control two performance specifications of equipment such as TSM: dimensional accuracy at specific particle sizes and uniformity of crystal circle scanning throughout the entire wafer scan. Calibration wafer standard wafers are typically provided in a fully deposited form with a single particle size (typically between 50nm and 12 microns). By depositing on the wafer, i.e. depositing, the wafer inspection system can lock particle peaks, and operators can easily determine whether tools such as SSIS meet performance specifications at this size. For example, if the wafer standard is 100nm and the peak value at 95nm or 105nm is detected in the SSIS scan, it can be determined that the SSIS exceeds the limit. At this time, a 100nm PSL wafer standard can be used for calibration. Scanning wafer standards can also inform technicians about the detection performance of SSIS in PSL wafer standards, thereby searching for similarities in particle detection among uniformly deposited wafer standards. The surface of the standard wafer is deposited with a specific PSL size, leaving no part of the wafer that has not been deposited on the PSL balls. During the scanning of PSL wafer standard wafers, the uniformity of the scanned wafers should indicate that certain areas of the wafer were not overlooked during the scanning process. Due to the different counting efficiencies of two different SSIS devices (deposition point and customer point), the counting accuracy on fully deposited wafers is subjective and one-sided, sometimes with a difference of up to 50%. Therefore, for the same standard piece, a count of 2500 particles with a size of 204nm was measured on the SSIS device 1, while the count values obtained from scanning on the customer's SSIS device 2 ranged from 1500 to 3000. The reason for the counting difference between the two SSIs devices is the different laser efficiencies of the internal PMT (photomultiplier tube). Due to the difference in laser power and laser beam intensity between the two SSIs devices, the counting accuracy between the two different wafer inspection systems is usually different.

Calibration wafer standard wafer
校正晶圆标准片校正晶圆标准片
The above two images show that there are two types of deposition for PSL calibration wafer standard wafers: full wafer deposition and multi-point deposition.

Polystyrene latex beads (PSL spheres) or silica nanoparticles can be deposited.

The PSL wafer standard with multi-point deposition is used to calibrate the size accuracy of the SSIS equipment at one or multiple size peaks.

The multi-point deposition calibration wafer standard has the following advantages: the spots formed by the PSL balls deposited on the wafer are clearly visible, and there are no remaining PSL balls on the surface of the wafer around the spots. The advantage is that over time, people can easily determine whether the calibration wafer standard cannot be used as a size reference standard due to being too dirty. Multi point deposition deposits the required PSL balls onto specific spot positions on the wafer surface; Therefore, the surface has very few PSL spheres and brings higher counting accuracy. Our company uses DMA (Differential Mobility Analyzer) technology for the 2300XP1 model to ensure accurate size peaks of the deposited PSL spheres. One CPC is used to control counting accuracy. DMA aims to remove unwanted particles from particle streams, such as double and triple sized particles. DMA is also designed to remove unwanted particles on the left and right sides of size peaks; Thus ensuring the deposition of dispersed particle peaks on the surface of the wafer. Without DMA technology, it is allowed to deposit unwanted double, triple, and background particles on the wafer surface, as well as the required particle size.