Heterogeneous Interface: The Achilles' heel of chip reliability

At the interfaces of multiple materials such as Cu/Ni and Ni/SnAg, issues such as interface brittleness, pore growth, and grain boundary weakening are highly prone to failure under thermo mechanical coupling loads. This has become a technological bottleneck that restricts the further development of high reliability and high-density packaging.

The research team from Southeast University has conducted a breakthrough study on the micro failure mechanism of flip chip bump interfaces using the in-situ TEM measurement system of Zeyou Technology. Their results have been published in the Journal of Materials Research and Technology.

Amazing intensity difference: 5-fold difference reveals weakest link

Through cantilever beam testing, the research team accurately measured the mechanical properties of two key heterogeneous interfaces in micro convex points. The experimental results are shocking: the tensile strength of the Cu/Ni interface is as high as about 1775 MPa, while the Ni/SnAg interface strength is only 335 MPa, a difference of more than 5 times.

Microscopic analysis shows that (Cu, Ni) ∝ Sn ₄ intermetallic compounds are formed at the Ni/SnAg interface, and there are numerous Kirkendall voids at the interface with SnAg solder, which is the main culprit for the significant decrease in interface strength.

In situ TEM: "Live Streaming" at the Nanoscale

The high-precision control capability of the in-situ TEM measurement system of Zeyou Technology enables researchers to capture the dynamic evolution process of the interface under load in real time.

In the study of Cu/Ni interface, fracture does not occur at the interface, but inside the Cu layer. The nano twin structure effectively hinders the propagation of microcracks, and the interaction of multiple slip bands ultimately forms a unique 'W' - shaped fracture path.

Ni/SnAg interface: void dominated failure mechanism

Under tensile load, the Ni/SnAg interface exhibits a unique failure mode of "void growth coalescence interface cracking". In situ TEM observation shows that the pre-existing Kirkendall voids at the IMC/SnAg boundary significantly expand under load, and then interconnect to form a continuous crack path.

These voids are mainly distributed on the side of IMC near the solder, attributed to the accumulation of vacancies caused by the difference in diffusion rates between Sn and Ni atoms. During the stretching process, the SnAg solder layer significantly extends and absorbs strain, while the Ni/IMC interface remains stable, confirming that the IMC/SnAg boundary is the weakest area in the entire structure.

Different behaviors under shear load

To simulate actual service conditions, the research team also conducted in-situ shear experiments. The results show that under shear loading, the Ni/SnAg interface exhibits different failure modes: cracks preferentially nucleate at IMC grain boundaries and trident grain boundaries, and propagate along the grain boundaries.

Unlike Kirkendall cavity dominated failure under tensile load, IMC coarse grains and their grain boundary defects become the dominant factors under shear conditions. This discovery indicates that refining IMC grains and enhancing grain boundary bonding strength are key ways to improve the reliability of micro convex point shear.

Technical insights: a leap from observation to regulation

This study not only reveals the microscopic mechanism of micro convex interface failure, but more importantly, establishes a quantitative system for micro interface strength, providing precise guidance for subsequent interface regulation and optimization.

By regulating the IMC structure and introducing process optimization methods such as nano twin strengthening, it is expected to achieve precise improvement in interface reliability. Zeyou Technology's in-situ TEM technology provides key support for this breakthrough, enabling researchers to achieve a transition from "observing phenomena" to "regulating performance" at the nanoscale.

With the continuous development of semiconductor devices towards miniaturization and high density, understanding and controlling the reliability of micro interfaces will become increasingly important. The advancement of in-situ characterization technology is opening a door for us to a more reliable and efficient world of chips.