1、 Core difficulty: Strict matching of dual channels (the most critical requirement)

The core application scenarios of digital dual channel filters, such as radar, ultrasound imaging, MIMO communication, and vibration analysis, require that the phase/amplitude distortion of the two signals be consistent (for example, by using dual channel differential amplification and phase difference measurement to infer physical quantities). Once the channels are mismatched, it will directly lead to measurement errors (such as phase difference offset, imaging blur, and inaccurate positioning). This is the core difference between it and single channel filters, and also the biggest design difficulty:

1. Amplitude matching error control

Requirement: The gain error of two channels for the same frequency signal should be controlled within ± 0.1dB~± 0.5dB (within ± 0.05dB for high-precision scenarios such as radar);

difficulty

On the hardware level, the gain deviation of two ADCs and the device tolerances (such as resistance and capacitance errors) of the analog front-end (amplifier, anti aliasing filter) will directly introduce amplitude mismatch, and temperature changes will exacerbate the deviation (such as resistance temperature drift causing gain drift);

Algorithm level: If adaptive filtering or nonlinear filtering algorithms are used, the iteration accuracy and parameter updates of the two algorithms will not be synchronized, which will result in inconsistent amplitude response under dynamic signals.

2. Phase/group delay matching error control

Requirement: The phase difference between the two channels should be controlled within ± 1 °~± 3 ° (within ± 0.5 ° for high-frequency scenarios such as above 1GHz), and the group delay deviation should be less than 1% of the signal period;

difficulty

Hardware delay differences: phase offset of ADC sampling clock, inconsistent PCB wiring length (even if the difference is 1mm, the phase difference of 1GHz signal is about 1.2 °), and phase nonlinearity of analog devices can all lead to fixed phase mismatch;

Algorithm delay difference: The selection of filter structure (such as FIRvsIIR), different order, or asynchronous operation timing of the two filters (such as the difference in pipeline number of the two filters in FPGA) can introduce dynamic phase deviation;

Nonlinear phase problem: IIR filters naturally have nonlinear phase, and even if designed as linear phase type, it is difficult to ensure that the phase curves of the two channels completely coincide, especially in the passband edge and stopband transition zone.

3. Timing synchronization error (sampling and operation synchronization)

Requirement: The sampling time deviation of the two signals should be less than 1/10 of the sampling period (i.e. synchronous sub sampling period);

difficulty

Sampling synchronization: If two independent ADCs are used, the allocation delay and jitter of the clock signal will cause a "sampling time skew" (i.e. time skew), even if the skew is 1ns, the phase difference of the 100MHz signal will reach 36 °;

Synchronization of operations: In processors such as DSP and FPGA, differences in the execution order of two filtering instructions and cache hits can lead to inconsistent computation delays, especially when dealing with large amounts of data or complex algorithms (such as high-order FIR filtering).

2、 Key difficulty: Conflict and balance of multi-objective performance

Single channel filters only need to optimize "passband ripple, stopband attenuation, and transition band width", while dual channel filters need to find a balance between "single channel performance", "channel matching", "real-time performance", and "resource consumption", which can easily lead to indicator conflicts:

1. Conflict between filtering performance and channel matching

Example 1: To improve the stopband attenuation of a single channel, it is necessary to increase the filter order (such as increasing the FIR filter from 128 to 256). However, the higher the order, the more sensitive the parameter deviation (such as coefficient quantization error) of the two algorithms is to phase matching, which may lead to increased phase mismatch;

Example 2: In order to reduce the passband ripple of a single channel, when using a window function to design an FIR filter, the quantization accuracy of the window function coefficients of the two filters is different (such as 16 bit vs 24 bit quantization), which can lead to inconsistent passband response and introduce amplitude mismatch.

2. Conflict between real-time performance and performance

Application scenarios: such as radar signal processing and real-time vibration monitoring, requiring a total delay (simulation+algorithm) of less than 1ms for dual channel filtering;

difficulty

Although linear phase FIR filters have good phase characteristics, they have high order and large computational complexity (N-order FIR requires N multiplications/additions), which increases computational delay. If low order FIR is used for compression delay, it will also result in insufficient stopband attenuation;

If an IIR filter is used (with low computational complexity and low delay), it will face nonlinear phase problems and significantly increase the difficulty of channel phase matching, especially in wideband signal processing.

3. Conflict between resource consumption and engineering implementation

difficulty

The coefficient storage and computational complexity of high-order linear phase FIR filters are twice that of single channels (such as 256 order FIR, which requires 256 coefficient storage per channel, a total of 512 coefficients in two channels, and doubles the computational complexity), placing higher demands on the logic resources of FPGA and the computational speed of DSP;

If adaptive channel equalization is used (such as using LMS algorithm to correct amplitude/phase mismatch), although it can improve matching accuracy, it will increase additional computational complexity and latency, which may exceed real-time requirements.